Senior Audio DSP Software Engineer

Codec, Voice AI, and NPU-Accelerated Audio

Employment Type: Full-time

About PIMIC

PIMIC is developing a next-generation low-power Audio AI co-processor platform for TWS, OWS, hearables, smart glasses, and other wearable audio products. Our architecture combines embedded audio processing, AI acceleration, and ultra-low power Processing-In-Memory technology to enable advanced voice, call, music, and contextual audio features at the edge.

Position Summary

PIMIC is hiring a Senior Audio DSP Software Engineer to help build and optimize the audio software stack for a next-generation low-power Audio AI co-processor.

The role includes codec porting, real-time playback and call pipelines, voice/audio processing, embedded DSP optimization, and integration with PIMIC's Processing-In-Memory NPU for audio AI workloads.

This is not limited to codec porting. The engineer will work on the boundary between traditional embedded audio DSP and NPU-accelerated audio AI, helping the team decide which functions should run on the

embedded DSP, MCU, hardware blocks, or PiM NPU.

The initial embedded DSP target includes Cadence Tensilica HiFi5s, but we are open to candidates with strong experience on other widely used embedded audio DSP platforms.

Why This Role Is Exciting

This role provides an opportunity to help define a new low-power audio AI co-processor architecture from early prototype through customer demo and production-oriented design.

The engineer will work on more than codec porting. They will help build the complete audio software pipeline around PIMIC's PiM NPU, including preprocessing, post-processing, buffering, scheduling, and validation for real-time voice and audio AI use cases.

The work includes hands-on embedded DSP optimization, but also broader architecture decisions such as:

  • Which workloads should run on the embedded DSP?

  • Which workloads should run on the PiM NPU?

  • How should audio frames, features, tensors, and inference results move through the system?

  • How do we meet real-time latency, memory, and power constraints in TWS and wearable products?

This gives the engineer a chance to work on codecs, voice enhancement, audio AI, embedded DSPs, and a differentiated NPU architecture in one role.

Key Responsibilities

  • Port and optimize audio codec and audio-processing software for embedded DSP platforms.

  • Work on codecs such as SBC, AAC, LC3, LC3plus, mSBC/CVSD, or similar, depending on project needs.

  • Optimize voice/audio processing blocks such as ENC, DNR, AEC, beamforming, EQ, SRC, gain control, limiter, and post-processing.

  • Vectorize and optimize performance-critical audio kernels using DSP SIMD/vector instructions, platform-specific intrinsics, fixed-point arithmetic, and memory-aware coding techniques to reduce cycle count, latency, and power.

  • Build and optimize real-time audio pipelines for music playback, call uplink/downlink, and demo audio flows.

  • Work with PIMIC's NPU, compiler, firmware, and model teams to partition audio workloads between embedded DSP, MCU, hardware blocks, and PiM NPU.

  • Develop and optimize audio preprocessing and post-processing pipelines around NPU-based inference workloads.

  • Support audio AI use cases such as ENC, DNR, KWS, speaker identification, event detection, and context-aware audio processing where DSP and NPU functions interact.

  • Define buffering, synchronization, tensor/audio-frame handoff, and scheduling between DSP software and NPU execution.

  • Profile and reduce cycle count, memory footprint, end-to-end latency, DSP utilization, NPU handoff overhead, and memory traffic.

  • Use DSP-specific optimization techniques such as SIMD/intrinsics, fixed-point arithmetic, memory alignment, scratch-memory placement, loop optimization, and compiler tuning.

  • Work with firmware, RTL, and system teams on DMA, ring buffers, shared SRAM, interrupts, mailbox/IPC, and multi-core audio pipeline integration.

  • Validate codec, DSP, and NPU-adjacent audio-processing output against reference implementations, golden vectors, simulator results, FPGA/prototype runs, and listening/demo requirements.

  • Produce performance reports, memory estimates, cycle estimates, porting notes, and known limitations documentation.

Required Qualifications

  • Strong C/C++ programming skills for embedded DSP, audio firmware, or real-time media systems.

  • Hands-on experience with audio DSP algorithms, codec software, or real-time audio pipelines.

  • Strong understanding of PCM audio, fixed-point processing, saturation, scaling, clipping, buffering, and latency.

  • Experience optimizing embedded software for cycle count, memory footprint, and real-time deadlines.

  • Experience optimizing and vectorizing fixed-point DSP kernels using SIMD instructions, platform-specific intrinsics, memory alignment, and cycle-level profiling.

  • Familiarity with audio processing blocks such as codec encode/decode, EQ, SRC, DRC/limiter, AEC, ENC, DNR, beamforming, or voice enhancement.

  • Experience with embedded build systems, cross-compilers, debuggers, simulators, profilers, and hardware bring-up environments.

  • Ability to validate outputs against golden/reference implementations and debug audio-quality or bit-exactness issues.

  • Ability to work closely with hardware, firmware, and algorithm teams in a pre-silicon or early silicon environment.

Preferred Qualifications

  • Experience optimizing audio software on widely used embedded DSP platforms such as Cadence Tensilica HiFi, CEVA DSPs, Qualcomm Hexagon, Arm Cortex-M/Helium, Synopsys ARC, or similar embedded audio/AI DSP architectures.

  • Experience with Cadence Tensilica HiFi5s, HiFi5, HiFi4, or HiFi3z is highly desirable.

  • Experience with vectorizing audio/DSP workloads on embedded platforms such as Cadence Tensilica HiFi, Arm

  • Helium/NEON, Qualcomm Hexagon, CEVA, or similar DSP architectures.

  • Experience with Xtensa Xplorer, Cadence toolchains, HiFi DSP libraries, cycle-accurate simulators, or related DSP development tools.

  • Prior work on Bluetooth audio codecs such as SBC, AAC, LC3, LC3plus, mSBC, CVSD, or similar.

  • Experience with TWS, earbuds, hearables, headsets, mobile audio, or low-power audio SoCs.

  • Familiarity with LE Audio, A2DP, HFP, LC3, AAC, and TWS call/music flows.

  • Experience integrating audio DSP software with MCU/RTOS environments.

  • Familiarity with DMA, mailbox/IPC, shared SRAM, ring buffers, and multi-core audio pipeline design.

  • Experience with FPGA prototype platforms, emulation platforms, or pre-silicon audio demos.

Nice to Have

  • Experience with audio-quality evaluation, subjective listening tests, PESQ/POLQA/STOI, SNR improvement, echo suppression, or noise suppression metrics.

  • Experience working with commercial codec libraries and licensing constraints.

  • Familiarity with AI audio workloads or integration of neural audio enhancement models.

  • Experience working with silicon bring-up, customer demos, or architecture feasibility studies.

What Success Looks Like

  • Audio codec and processing software runs correctly on the target embedded DSP platform.

  • Music playback and call-path workloads meet real-time frame deadlines.

  • DSP preprocessing/post-processing integrates cleanly with PIMIC's PiM NPU inference path.

  • Cycle count, memory footprint, latency, and utilization are measured and documented.

  • Codec, DSP, and NPU-adjacent audio-processing outputs are validated against reference/golden outputs.

  • The team has clear data to decide which functions should run on the DSP, MCU, NPU, or hardware blocks.

  • The engineer helps create a reliable demo and production-oriented software path for the audio co-processor platform.

Suggested Candidate Background

  • Audio DSP teams at semiconductor companies.

  • Bluetooth audio, codec, or voice-processing companies.

  • Mobile SoC or TWS audio firmware teams.

  • Cadence Tensilica, CEVA, Qualcomm Hexagon, Arm Helium, Synopsys ARC, or other embedded DSP development teams.

  • Hearables, headset, wearable, or edge AI audio companies.

What We Offer

  • Work on production-oriented edge-AI technology from model import through silicon execution.

  • A collaborative environment with significant technical ownership and impact.

  • A competitive compensation package including stock options

Location

  • India or USA. Position could be located anywhere in these two countries (remote), or in-person in Chennai or the Bay Area

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